1. Field of the Invention
The present invention relates to a technology used for a driver circuit provided in the output stage of an interface unit transmitting signals to the device/circuit disposed after the driver circuit for driving the device/circuit, more particularly to a technology of a driver circuit, capable of adjusting the driving capacity of the device/circuit disposed after the driver circuit.
2. Description of the Related Art
As a device whose driving capacity must be adjusted by the driver device, there is, for example, a memory interface based on the DDR2 (double data rate 2) rating stipulated by JEDEC (Joint Electron Device Engineering Council).
The adjustment of the driving capacity of a driver circuit in the memory interface is described with reference to FIG. 1. In this memory interface, four bits of control signal is inputted to both the power supply side (P-channel type metal oxide semiconductor (MOS) transistor side) and ground side (N-channel type MOS transistor side) of a driver circuit 101 for driving memory 200 provided for a controller 100, and it is required that the driving capacity can be adjusted by the four bits (at 16 steps).
One configuration of the conventional driver circuit capable of adjusting such a driving capacity is shown in FIG. 2.
In this configuration, n sets of a pairs of two P-channel type MOS transistors whose source terminal and drain terminal are connected in series are provided between a power supply line 110 and an output signal line 130. Furthermore, n sets of a pair of two N-channel type MOS transistors whose source terminal and drain terminal are connected in series are provided between a ground line 120 and an output signal line 130.
A signal input line 140 is connected to the input terminal of a pre-driver 150, and the output of the pre-driver 150 is commonly connected to all the gate terminals of both the P-channel type MOS transistors (hereinafter simply called “P type transistor”) 111-1, 111-2, . . . , 111-n and the N-channel type MOS transistors (hereinafter simply called “N type transistor”) 121-1, 121-2, . . . , 121-n. Therefore, the pre-driver 150 collectively controls the on/off of each of these MOS transistors (hereinafter simply called “transistor”) according to the theory of a digital signal (transmission signal) inputted to the signal input line 140.
A control signal for adjusting the driving capacity on the power supply side of the driver circuit 101 is connected to the gate terminal of each of the P-type transistors 112-1, 112-2, . . . , 112-n through a power supply side control signal line 170, and a control signal for adjusting the driving capacity on the ground side of the driver circuit 101 is connected to the gate terminal of each of the N-type transistors 122-1, 122-2, . . . , 122-n through a ground side control signal line 180. The on/off of these transistors is controlled based on a control signal inputted to the power supply side control signal line 170 or the ground side control signal line 180.
In this case, the number of transistors simultaneously switched on by this control signal is set based on the value (one value in 16 steps) of the control signal. Since by doing so, the number of transistors engaged in the driving of the memory 200 connected to the output signal line 130 can be controlled by the value of this control signal, the driving capacity of the driver circuit 101 can be adjusted.
A technology for forming a driver circuit for providing P-type and N-type transistors between the power line and the output signal line and between the ground line and the output signal line is disclosed in Japanese Patent Application Nos. 2003-218689, 2001-196916 and 2002-190729.
In FIG. 2, since a pair of two P-type transistors connected in series and a pair of two N-type transistors connected in series must be arrayed in parallel, a lot of transistors are needed to form the driver circuit 101. Therefore, a wide area is needed to form the driver circuit 101 on a semiconductor substrate.
If the control signal for designating the driving capacity of the driver circuit 101 is given as parallel data, a circuit for converting the parallel data to generate a signal to be applied to each gate terminal of the P-type transistors 112-1, 112-2, . . . , 112-n and the N-type transistors 122-1, 122-2, . . . , 122-n is also needed.